Get In Touch With Us!
Our dedicated team is here to provide you with prompt and efficient support to address any inquiries or concerns you may have regarding NeuLink’s products or services
Our dedicated team is here to provide you with prompt and efficient support to address any inquiries or concerns you may have regarding NeuLink’s products or services
Dr. Naveed Sherwani is a well-known semiconductor industry veteran with over 35 years of entrepreneurial, engineering, and management experience. He is widely recognized as an innovator and leader in the field of design automation of ASICs and microprocessors. Naveed has founded or co-founded over fifteen silicon companies which collectively have a valuation of over $ 4.5B.
Throughout his illustrious career, Naveed has demonstrated remarkable fundraising acumen, securing over $1 billion across 15 funding rounds from prestigious venture capital firms. His leadership has earned accolades, with Naveed being recognized as the leader of the "Most Respected Private Semiconductor Company" an unprecedented five times by the Global Semiconductor Alliance (GSA), the premier semiconductor industry membership body. Currently, Naveed serves as the Chairman of GS Group, where he spearheads initiatives to drive the next wave of silicon innovation and facilitates growth strategies for semiconductor companies. Additionally, he holds an advisory role with the American Frontier Fund (AFF).
In recent years, Naveed has played a pivotal role in catalyzing the global adoption of the RISC-V architecture during his tenure as Chairman, President, and CEO of SiFive. Under his guidance, SiFive underwent remarkable growth, evolving from a 20-person startup valued at approximately $20 million to a global entity with over 500 employees and a valuation surpassing half a billion dollars. Notably, he co-founded a Federation comprising four other silicon companies (StarFive, SemiFive, LeapFive, and ChinaFive), each strategically focused to maximize the value creation and adoption of RISC-V. This Federation, under Naveed's leadership, raised over $350 million through eleven financing rounds, collectively reaching a valuation exceeding $1.3 billion.
In 2003, Naveed co-founded Open-Silicon, an innovative company that streamlined ASIC development processes and reduced ownership costs. With investments totaling $45 million from prominent VCs such as Sequoia, Norwest, and Interwest, Open-Silicon was successfully exited at $252 million in a sale to a private equity group.
From 1993 to 2003, Naveed held various positions at Intel, commencing with design technology and culminating in the role of General Manager of Intel Microelectronics, a division he co-founded. His tenure witnessed the implementation of Athena, a transformative system that greatly enhanced automation in microprocessor projects. Naveed was honored with the prestigious Intel Achievement Award.
He served as a professor at Western Michigan University from 1988 to 1993, where his research encompassed ASICs, EDA, combinatorics, graph algorithms, and parallel computing. He authored several books and over 100 articles on VLSI Physical Design Automation and ASICs. His seminal work includes the widely adopted textbook, "Algorithms for VLSI Physical Design Automation," a standard in graduate courses at leading universities worldwide. Naveed also authored over 125 technical articles on various aspects of VLSI physical design automation and ASICs, several of which received best paper awards. Naveed earned his PhD in computer engineering from the University of Nebraska, Lincoln, focusing on the application of graph algorithms for chip design automation.
Dr. Shafy has 40 years of experience in the semiconductor industry, working with ASIC, FPGA, Analog Mixed Signal, and Memory Technologies. As CEO of OpenFive, a SiFive BU, he managed a team of 350 employees developing custom chips, RISC-V core processors, and connectivity IP's for various applications. Prior to that, he held VP positions at Microsemi, Open Silicon, and Lightspeed Semiconductor, where he played important roles in the development of ASIC, SoC, and structured ASIC/FPGA products. Dr. Shafy holds a Ph.D. in Electrical Engineering from the University of Waterloo and M.Sc., B.Sc. in Electrical Engineering from Cairo University.
Bhavin is a seasoned executive with over 25 years of experience in the world of technology, specializing in product development across a diverse range of industries, including semiconductors, Artificial Intelligence (AI), Programmable computing, and computer networking. His career is marked by a relentless pursuit of excellence and innovation, consistently delivering solutions that not only drive revenue growth but also enhance operational efficiency in fast-paced environments.
Bhavin's reputation as an industry expert is well-deserved. Throughout his career, he has been at the forefront of key growth initiatives, leading teams to success in various cutting-edge sectors. His ability to identify and capitalize on emerging trends has consistently propelled him to the forefront of technological innovation.
Bhavin's leadership prowess is evident in his proven track record of building and guiding highly motivated teams across multiple countries. His collaborative leadership style fosters an environment where individuals thrive, resulting in exceptional team performance. He is highly regarded for his work ethic, problem-solving skills, and effective communication, making him a sought-after leader in the industry.
At NeuLink Semiconductor, Bhavin serves as CEO, where he continues to drive innovation and growth. Prior to this role, he spent two successful years as the Senior Vice President of Engineering at Rapid Silicon, where he oversaw all aspects of engineering. During his tenure, Bhavin achieved a remarkable milestone by building a global team of over 140 engineers. His team's groundbreaking achievement was the development of the world's first commercial embedded FPGA IP, complemented by an EDA software suite based on open-source technology.
Before his time at Rapid Silicon, Bhavin dedicated over a decade to Quantenna, a company that was later acquired by onsemi. There, he led the development of WiFi-based IoT Client solutions and Access Point SoCs, solidifying his reputation as a pioneer in wireless technology.
Prior to Quantenna, Bhavin held influential roles in SoC development at renowned companies like Sibridge, Ikanos, VxTel, and eInfochips. His diverse experiences in these positions enriched his understanding of technology development and innovation.
Bhavin's academic foundation includes an MSEE (Master of Science in Electrical Engineering) from San Jose State University and a BSEE (Bachelor of Science in Electrical Engineering) from Gujarat University.
Alain Dargelas, Ph.D., Neulink's SVP Software, has over 30 years of EDA experience.
He is highly experienced in both FPGA and ASIC EDA SDKs, Digital/Analog Design Analysis and Linting software stacks, Verification and Debugging software stacks, Synthesis & P&R software stacks and finally GUI.
Alain earned his Ph.D. in Automatic Test Pattern Generation working concurrently for Compass Design Automation in 1997. He is a major contributor to the open-source community in the space of SystemVerilog compilation and FPGA SDK.
Alain recently architected and created an organization of 55+ engineers across 8 countries around the globe in order to create RapidSilicon's Raptor Design Suite SDK.
Raptor SDK uses components from the open-source like: SystemVerilog and VHDL parsers, RTL Synthesis, Place-and-Route, Bitstream generation, Firmware-based Configuration, Simulation, Graphical User Interface, Command interface, Device Programming and Debugging and FPGA Device modeling.
Prior to NeuLink Semiconductors, Alain spent 8 years at Altera/Intel managing, in turn, different teams responsible for most aspects of FPGA configuration, from Device Modeling to Physical Synthesis.
Alain has also held Senior Management and Technical Lead positions at Synopsys, Atrenta, Knowlent, Avant!, InterHDL and Compass Design Automation, working on various ASIC EDA SDKs.
He is holding several Patents in Design Analysis, specifically on Multi-clock domain Verification, and has published in major conferences papers on Automatic Test Pattern Generation.
Zarin has over 20 years of experience in the high-tech industry in various engineering and executive roles. At NeuLink, Zarin works as SVP, Product Development and is responsible for the execution of all products from tape-out to productization.
Prior to Neulink, Zarin worked at Rapid Silicon as Vice President of Program Management & IT, where she managed cross-functional product development of FPGA/SoC 100KLE devices. Zarin worked in the Wi-Fi connectivity division of Onsemi before joining Rapid Silicon, where she managed the Wi-Fi client chip program to enable IoT, automotive & industrial markets, RF/Baseband chipsets qualification, and successful deployment of 802.11ac 10Gbps complex access point chipset in one of the largest US-based ISP. She has played an integral part in Onsemi/Quantenna integration.
Zarin has helped build and fostered strong global teams across multiple geographies. Zarin holds a Bachelor of Science degree in Computer Science from IIU University.
With almost four decades in semiconductors, mostly in design and automation for ASICs, structured ASICs, and FPGAs, Dana How has led or contributed to the development of architectures based on SRAM-, anti-fuse-, and single-mask-configurable technologies, holding technical leadership positions at Lightspeed Semiconductor, Monterey Design Systems, Cswitch, and Altera/Intel PSG.
His career started in automated software retargeting, and in two CMOS imaging ventures he was responsible through acquisition for digital design and automation as well as characterization and operations. Stanford University issued his doctorate and master’s degrees and Yale University his bachelor’s degree, and he has forty-two patents and several refereed publications.
Rob is an experienced ASIC designer with domain knowledge in networking, wireless, graphics, and audio. He has a track record of shipping successful products, including the Catalyst 9K Ethernet switch at Cisco. Recently he has been applying ML and deep learning algorithms to solve challenging problems in image processing, Wi-Fi PHY/MAC optimization, and IoT.
His current focus is unlocking the massive parallelism in deep model evaluation using pure Verilog. Rob received a BSEE from Princeton University.
Brian Philofsky is a 28-year industry veteran serving leadership roles in several engineering design and customer-facing roles. Prior to his current role, Brian was the Sr Principal Engineer responsible for product and architecture planning as well as chief power architect at Rapid Silicon. At Xilinx/AMD, Brian was responsible for the overall power and thermal strategies across all of its products: silicon, software/tools, SOMs and boards. Driver of FPGA-centric power reduction techniques and initiatives for leading edge designs in automotive, aerospace and defense, wired, wireless, industrial, prototype and emulation, data center and several other key markets.
He is the inventor of 13 US patents concerning digital simulation, synthesis, timing, power optimization and thermal design, co-author of the book “Designing with Xilinx® FPGAs: Using Vivado” as well as several IEEE papers, technical trade magazine articles, application notes and technical manuals for many aspects of FPGA design/verification, PCB design and thermal design.
Liwu has more than 24 years of chip design experience of multiple major CPU/GPU/FPGA/Network product series in the semiconductor industry. Before joining Neulink, Liwu served as the Vice President of Silicon Engineering at Rapid Silicon. He has over 20 successful tapeout projects at Intel, Altera, Nvidia, Freescale, and Sun Microsystem.
Liwu has built self-motivated multiple global teams from scratch and trained the teams to execute projects flawlessly and deliver on time. he has been responsible for every step of projects, from budget and resources, design, methodology, DFT, and packaging, to silicon validation. His design experience spans all areas of chip development.
Liwu holds a master's degree in electrical engineering from the University of Michigan.
Jayaprakash Mannem has over 30 years of semiconductor industry experience in IP & SoC chip design and development across various domains. He has worked extensively on processors, AI engines, servers, accelerators, Wi-Fi technology, and coherent fabric. His career spans across several prominent companies in the tech industry, including Onsemi, Xilinx, Intel, Cray, IBM, Newisys, and HaL.
Before his current role as Vice President of ASIC Engineering at NeuLink Semiconductors, Jayaprakash Mannem led the development of Client Wi-Fi Chips at Onsemi's QCS division. He has also held various technical leadership & management positions in chip development at Xilinx, Intel, and IBM.
He holds a Master's degree in Computer Engineering from Wayne State University and a Bachelor's degree in Electrical & Electronics from Kakatiya University.
Senior Human Resources professional with 20+ years of experience in high-technology. A demonstrated track record in many disciplines of HR including compensation, benefits, talent acquisition, immigration, coaching, and employee relations. A key member of the business leadership team and trusted advisor to C-level and senior managers.