Application Specific Programmable Devices
Modular Device Architecture Enables Rapid Development
Our Application Specific Programmable Devices (ASPD) offer a competitive edge, optimizing performance and efficiency while reducing costs and accelerating time-to-market. Featuring reusable SoC & IO blocks and scalable FPGA fabric, our ASPDs can be tailored for a variety of applications, meeting both current and future needs. Transformable ASPDs find applications in:
– Sensor Fusion, Robotics, Industrial Automation
– Machine Vision, Surveillance, & Medical Imaging
– AR/VR Systems, Predictive Maintenance, Agriculture Automation
– Automotive Infotainment, ADAS, Functional Safety
– Network Bridging & Data Processing
A Strategic Roadmap for Low to High-Range ASPDs Suitable for Any Application
NeuLink is developing a wide range of Application Specific Programmable Devices for multiple applications. Leveraging our NeuFPGA-based FPGA Complex alongside FlexNoC integrated Processor Complex, we are building variants tailored for various applications. Our ASPDs differentiate themselves with different combinations of High-Range I/Os, High-Performance I/Os, and Multi-protocol Transceiver Sub-systems
Rapid application development is supported on these devices through the Raptor Design Suite, enabling FPGA Complex programming, providing a development platform for the Processor Complex, and offering integrated simulation for performance evaluation before implementation
FPGA Complex
Our FPGA Complex comprises CLB, BRAM, and DSP blocks forming the base functionality. Connected via a robust clocking network, it supports up to 16 clocks and 4 PLLs, enabling clocking performance up to 500 MHz and logic-level design performance exceeding 300 MHz. The Raptor Design Suite implements front-to-back FPGA design, featuring efficient synthesis and producing high-performance results
Processor Complex
Tightly integrated with the programmable fabric is a powerful RISC-V-based processor subsystem for entry-level ASPDs, scaling up to quad-core A-series Arm Processor for high-end ASPDs
Complemented by a 16/32-bit hardened DDR controller (scalable up to 32/64-bit DDR Controller), supporting LPDDR3/DDR3, LPDDR4/DDR4, and DDR5 memories. The Processor Complex features multiple peripherals like SPI/QSPI, JTAG, I2C, UART, Timer, and DMA Engines to extract its high-performance capacity
The entire Processor Complex interconnects with Network On Chip (FlexNoC), providing smooth integration with FPGA Complex
IO Complex
The IO Complex consists of 3 types of IOs : High Range I/Os (HRIO), High Performance I/Os (HPIO) and Multi-protocol Transceivers (MPTRx)
HRIO supports wide range of single-ended I/O standards, including LVCMOS with different drive strengths, LVTTL, SSTL, PCI66, and PCIX133. Additionally, they support a variety of differential I/O standards, such as LVDS, LVPECL, BLVDS, and RSDS
HPIOs are best fit for applications requiring performance up to 1.6 Gbps with a voltage range of 1.2V to 1.8V. They also support of single-ended I/O standards, including LVCMOS with various drive strengths, HSTL, SSTL, HSUL, and POD. Additionally, they support a variety of differential I/O standards, such as LVDS, SGMII, DIFF_HSUL, DIFF_POD, SLVS, and MIPI
MPTRx is built using a multi-protocol transceiver capable of speeds up to 16 Gbps, with a multi-protocol PCS developed in-house. It supports a wide range of high-speed protocols, including MIPI, HDMI, PCIe Gen1-4, XGMII, and USB3.x. There are plans to upgrade MPTRx to support PAM-4 and achieve a throughput of 64 Gbps to support protocols like PCIe Gen5/6 and CXL2/3.x in the future
Configuration
A RISC-V-based configuration engine securely and efficiently loads the configuration bitstream data to the device to realize its end functionality. Being RISC-V allows additional customization to the loading and configuration of the FPGA that many other devices cannot offer. The configuration sub-system has an SPI/QSPI interface for configuration data storage and several other interfaces (JTAG, UART, I2C) available for debug and configuration engine communications. The configuration circuitry has an optional PUF with 256-bit AES encryption for secure bitstream storage
Packaging
NeuLink uses lidded and lidless flip-chip packaging, utilizing on-package capacitors and optimized ball layouts for high-performance, small-footprint devices that require fewer additional passive and active components on the board. Both the lidless and lidded packages offer superior thermal dissipation, reducing cooling needs. The optimized BOM generally results in a very cost-optimized and board area-efficient design
Making EDA Software Accessible to All Through the Raptor Design Suite
NeuLink is at the forefront as the inaugural PLD company to embrace and implement open-source development software, leveraging the Raptor Design Suite tool. This move unlocks the potential of a thriving community, fostering a vast ecosystem for innovation, development, support, and large-scale deployment. The democratization of the software development toolchain accelerates innovation and cultivates a collaborative support network, collectively striving to make NeuLink’s EDA environment unparalleled in the industry
Discover more about NeuLink’s pioneering open-source EDA tool, the Raptor Design Suite, and its role in democratizing PLDs